1. Field of the Invention
The present invention relates to methods of providing a shallow trench in a deep-trench device.
2. Brief Description of the Background Art
Isolation of deep-trench capacitors by means of a shallow isolation trench is a well-known step in the formation of semiconductor devices, and in particular dynamic random access memory (DRAM) devices.
FIGS. 1A-1C illustrate a prior art procedure for trench capacitor isolation. Turning to FIG. 1A, a trench capacitor structure is illustrated, which includes a silicon wafer 110 having trenches that are lined with an oxide layer 114, such as a silicon oxide layer or an ONO layer, and are filled with doped polysilicon regions 116. Portions of the upper surface of the silicon wafer 110 are provided with pad oxide regions 118, upon which silicon nitride regions 120 (which previously acted as a part of the trench masks) are disposed. An anti-reflective coating 122 is provided over this structure, which is in turn covered with a patterned photoresist masking layer 124.
Using photoresist masking portions 124 as a trench mask, trench isolation is initiated by anisotropically etching through the anti-reflective coating 122 and through the nitride regions 120 to reveal portions of the silicon wafer 110 and the polysilicon regions 116. The resulting structure is shown in FIG. 1B.
Subsequently, the structure is etched until the oxide layer 114 lining the trenches is reached. To achieve a substantially flat trench bottom, as exemplified in FIG. 1C, a plasma source gas, such as CF4/CHF3/Cl2, is selected that will provide approximately 1:1:1 silicon:polysilicon:oxide selectivity and adequate passivation. A trench with a flat bottom is desirable, for example, to prevent shorting upon the deposition of further layers, for example, in the course of DRAM production. Unfortunately, such 1:1:1 selectivity is, in practice, difficult to achieve, particularly if one wishes to concurrently have control over the etch profile within the isolation trench.
The above and other difficulties of the prior art are overcome by the present invention.
According to a first embodiment of the present invention, a method of forming a shallow trench within a trench capacitor structure is provided. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of  less than 1:1:1 and (b) a second plasma etching step having an oxide:silicon:polysilicon selectivity of  greater than 1:1:1, more preferably  greater than 1.3:1:1.
Preferably, the first and second plasma etching steps are conducted using plasma source gases that comprise halogen-atom-comprising species and are conducted within a decoupled plasma source etching system.
The first plasma etching step is preferably conducted using a plasma source gas that comprises at least one halogen containing species selected from CF4, CHF3, HBr and Cl2. For example, the first plasma etching step can be conducted using a plasma source gas that comprises Cl2, HBr and O2, more preferably 10 to 20% Cl2, 70 to 88% HBr, and 2 to 6% O2. As another example, the first plasma etching step can be conducted using a plasma source gas that comprises CHF3, CF4 and Cl2, more preferably 45 to 75% CHF3, 15 to 35% CF4, and 10 to 25% Cl2.
The second plasma etching step is preferably conducted using a plasma source gas that comprises a noble gas and a halocarbon, with preferred halocarbons being of the formula CxXyHz, where X is a fluorine atom, x is an integer of 1 to 2, y is an integer of 1 or more, and z is an integer of 0 or more. For example, the second plasma etching step can be conducted using a plasma source gas that comprises CF4 and Ar, more preferably 30 to 50% CF4 and 50 to 70% Ar. In some cases, the plasma source gas further comprises CHF3.
Typically, within this first embodiment of the present invention, the first plasma etching step will result in protrusions along the trench bottom at the interfaces with the first and second oxide regions, with the protrusions being from 50 to 300 Angstroms in height.
In another embodiment, the first plasma etching step has a oxide:silicon:polysilicon selectivity of  greater than 1:1:1 and the second plasma etching step has an oxide:silicon:polysilicon selectivity of  less than 1:1:1. This typically results in depressions along the trench bottom at the interfaces with the first and second oxide regions, the depressions being from 50 to 300 Angstroms in depth.
An advantage of the present invention is that a process is provided which provides a shallow trench, which can function as an isolation trench, with a substantially flat trench bottom, while at the same time providing greater flexibility with respect to etch profile than prior processes.
The above and other embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon reading the detailed description and claims to follow.